TTTC's Electronic Broadcasting Service

ITC 2014 - CALL FOR TUTORIALS PARTICIPATION

Scope

The Test Technology Educational Program (TTEP�14) of the TTTC is offering 12 half-day tutorials during the weekend before the ITC test week. This year, the TTEP tutorials will touch the most important topics of the test scenario, problems and solutions taught by recognized experts of the field.

You can get detailed information on the TTEP website: http://ttep.tttc-events.org/ttep/tutorials.html

Registration

Register for Test Week Tutorials at the ITC Registration Page http://itctestweek.org/register.

Conference, tutorial and workshop registration can all be done with our easy to use on-line registration form.

Early registration is approaching: 26th September 2014!!

Program

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October 19, 2014 (Sunday)

08:30AM - 12:00PM (Tutorial 1) Testing of TSV-Based 2.5D- and 3D-Stacked ICs - Basic

by E.J. MARINISSEN, K. CHAKRABARTY

Stacked ICs with fine-pitch micro-bumps and through-silicon vias offer heterogeneous integration, increased performance at lower power consumption, and potentially lower product cost. However, testing for defects remains an obstacle and potential showstopper. In this basic tutorial, we present key concepts in 3D technology, terminology, and benefits. We also discuss test challenges and emerging solutions. Topics to be covered include an overview of 3D integration and trendsetting products such as a 2.5D-FPGA and 3D-stacked memory chips, test flows and test content for 3D chips, advances in wafer probing, modular testing and design-for-test architectures, and ongoing IEEE P1838 standardization efforts.

08:30AM - 12:00PM (Tutorial 2) TMixed-signal DfT & BIST: Trends, Principles, and Solutions

by STEPHEN SUNTER

We analyze recent trends in IC processes and design, and implications for test,then look at trends in testing. Next, we discuss trends in ad hoc DFT and fault simulation, then IEEE DFT standards 1149.1, .4, .6, .7, .8, P1149.10, and P1687. The trend analysis concludes with a review of BIST techniques. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and (briefly) RF. Next, seven essential principles of practical analog BIST are presented. Lastly, we discuss practical DFT techniques, ranging from analog defect simulation and classic analog bus, to oversampling and undersampling methods that greatly improve range, resolution, and reusability.

08:30AM - 12:00PM (Tutorial 3) Hardware Security and Test

by R. KARRY, Y. MAKRIS, M. POTKONJAK, O. SINANOGLU, P. SONG

In this tutorial, we expose the vulnerabilities of today�s globalized IC design and manufacturing flow, review the security threats, show that we can adapt techniques from VLSI testing to cope with these threats, and review design-for-trust techniques. We provide a brief survey of process variation and device aging with an emphasis on current technologies and pending trends, and elaborate on the ramifications of process variation, device aging, and gate level characterization on several security tasks including resilience against timing, electromagnetic, and power attacks, malicious circuitry detection, diagnosis, and masking, IC counterfeiting detection, and the creation of hardware security primitives, such as physical unclonable functions (PUFs), public PUFs, and random number generators. Finally, we review the ongoing hardware security efforts at IBM TJ Watson Research Labs.

01:00PM - 04:30PM (Tutorial 4) Testing of TSV-Based 2.5D- and 3D-Stacked ICs - Advanced

by E.J. MARINISSEN, K. CHAKRABARTY

Stacked ICs with fine-pitch micro-bumps and through-silicon vias offer heterogeneous integration, increased performance at lower power consumption, and potentially lower product cost. However, testing for defects remains an obstacle and potential showstopper. In this advanced tutorial, we present a brief overview of 3D technology, terminology, and benefits, and provide detailed coverage of 2.5D/3D test challenges and emerging solutions. Attendees are expected to have some familiarity with 2.5D/3D test techniques. Topics to be covered include: (i) 3D test access architectures for logic-on-logic chips, and memory-on-logic chips with JEDEC Wide-I/O, DfT for 2.5D chips, and EDA flows and industry case studies; (ii) DfT optimization and repair techniques; (iii) innovations in wafer probing and alternatives to probing for pre-bond test; (iv) 3D test-cost modeling and test-flow selection.

01:00PM - 04:30PM (Tutorial 5) Practices in High Speed I/O Testing

by S. ABDENNADHER, S. A SHAIKH

With the increasing number of IO�s and greater data rates, significant challenges arise for testing high-speed interfaces (HSIO) in terms of test cost and quality. This tutorial presents existing industrial techniques to meet the ever increasing test complexity of these Interfaces. It first describes the basic design of both serial and parallel HSIO (e.g. PCIe and DDR) and presents their various testing methods, such as Eye margining, Compensation testing, leakage testing, ... The examples of all these test methods will be presented with special emphasis on DFT and BIST based approaches of HSIO testing and their suitability to production environment.

01:00PM - 04:30PM (Tutorial 6) Delay Test: Concepts, Theory and Recent Trends

by S. NATARAJAN, A. SINHA

This tutorial covers fundamental concepts, recent ideas and industry practices on validating and testing integrated circuits for speed failures. Main areas covered are: (a) defects and marginalities such as crosstalk, voltage droop, multiple-input switching and charge-sharing that result in speed failures, (b) delay fault models and fault sensitization conditions, (c) classical and advanced metrics to measure delay test quality and methods to improve them, (d) design-for-test to facilitate application of delay tests, (e) algorithms for test generation, fault simulation and diagnosis, including cell-aware and those targeting memory shadow and time borrowing logic, and (g) applications in post-silicon validation, speed binning and in-field reliability using industry case studies.

October 20, 2014 (Monday)

08:30AM - 12:00PM (Tutorial 7) Hierarchical Test for Today�s SoCs

by Y. ZORIAN

Today�s SOC design teams, from mobile applications to Internet of Things (IoT), use multi-level hierarchical architectures to handle design size explosion, liberal use of 3rd-party IPs, and multi-level hierarchical blocks (IPs, cores, sub-chips, SOC). To test such SOCs, DFT designers adopt new hierarchical test solutions across heterogeneous cores (memories, logic, AMS and interface IP), in order to support concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500 and P1687, along with intelligent infrastructure IP to help achieve the above advantages.

08:30AM - 12:00PM (Tutorial 8) Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability

by A. SINGH

Commercial applications continue to demand ever higher IC quality, most notably a �zero defect� target from automotive manufacturers. To cost effectively meet this challenge, innovative new statistical screening techniques improve test effectiveness by first identifying �suspect� parts, that are then more extensively tested, sometimes using tests that specifically target the suspected failure modes. Such adaptive tests exploit statistical correlations in process, performance and defect parameters. This tutorial presents a range of such test methodologies, and illustrates their effectiveness with results from recently published studies on production parts. Commercial tools from new companies in the "Adaptive Test" space are also discussed.

08:30AM - 12:00PM (Tutorial 9) Test, Diagnosis, and Root-Cause Identification of Failures for Boards and Systems

by K. CHAKRABARTY, W. EKLOW, Z. CONROY

The gap between working silicon and a working board/system is becoming more significant as technology scales and complexity grows. The result of this increasing gap is failures at the system level that cannot be duplicated at the component level. These failures are most often referred to as �NTFs� (No Trouble Founds). The problem will only get worse as technology scales and will be compounded as new packaging techniques (SiP, SoC, 3D) extend and expand Moore�s law. This tutorial will provide detailed background on NTFs and will present DFT, test, and root-cause identification solutions at the board/system level.

01:00PM - 04:30PM (Tutorial 10) Hierarchical SCAN Compression

by Y. HUANG, B. KELLER, A. CRON

This tutorial covers fundamental concepts, recent developments and industry practices on scan compression in SoC hierarchical test flow. The tutorial starts with a discussion on compression technologies for a single design, followed by hierarchical DFT methodologies and techniques such as TAM / wrapper / test scheduling, diagnosis etc. IEEE test standards such as 1149.1, 1500 and P1687 will be introduced. Finally it demonstrates the latest hierarchical compression technologies, flows and solutions from three leading EDA companies. Each company introduces its own complete DFT and ATPG flow to integration the state-of-art compression technologies into the hierarchical core based SoC designs.

01:00PM - 04:30PM (Tutorial 11) Memory Test and Repair in Nanometer Era

by M. D�ABREU, Y. ZORIAN

Recent growth in content creation has led to an explosion in the use of embedded memories. This tutorial will present a range of memories used, including RAMs and Non-Volatile memories (Flash) and how to ensure detection of today�s defects upon manufacturing and during life time, including process variation and FinFET specific defects. BIST and Repair solutions to address yield optimization, endurance and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today�s SOCs, the tutorial will also cover power management constraints, functional timing implications, test scheduling optimization, and area minimization options.

01:00PM - 04:30PM (Tutorial 12) Practices in RF IC Testing

by S. ABDENNADHER, S. A SHAIKH

This tutorial presents existing industrial techniques for testing the RF ICs and SoCs in the production environment. These techniques involve ATE and other instrumentation but greatly rely upon on-chip DFT and BIST structures. The tutorial first introduces the basic concepts associated to RF measurements, such as power compression, harmonics, ISI, noise figure, phase noise, BER, and EVM. Later, the tutorial presents the contemporary examples of ATE-based and DFT/BIST-based testing techniques for RF transceivers. At the end of the tutorial describes the testability of the newer design trends in RF systems such as MIMO, LTE, NFC and SiP based systems.

Additional Information

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Paolo Bernardi

TTEP Vice Chair (Program)
Politecnico di Torino, I
Tel.: +39 011 564 7183
Fax: +39 011 564 7099
Email: paolo.bernardi@polito.it

Committee

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VICE CHAIR (PROGRAM)

P. BERNARDI � Politecnico di Torino

PAST CHAIR

D. GIZOPOULOS � University of Athens

FINANCE CHAIR

C.-H. CHIANG � Alcatel-Lucent

PUBLICITY CHAIRS

G. DI NATALE � LIRMM
E. SANCHEZ � Politecnico di Torino

PLANNING CHAIR

Y. ZORIAN � Synopsis

INDUSTRIAL RELATIONS CHAIR

R. GALIVANCHE � INTEL Corporation

AUDIO/VISUAL CHAIRS

S. MENON � INTEL Corporation
O. SINANOGLY � NYU in Abu-Dhabi

ELECTRONIC MEDIA CHAIRS

S. DI CARLO � Politecnico di Torino
A. BOSIO � LIRMM

ORGANIZING LIASONS

F. FUMMI � DATE'14
D. GIZOPOULOS � LATW'14
S. RAVI � VTS'14
Y. ZORIAN � ITC'14
Y. ZHANG � ATS'14

PROGRAM COMMITTEE

Robert C. Aitken � ARM, USA
Davide Appello � STMicroelectronics, I
Kanad Chakraborty � Lattice Semiconductor, USA
Sreejit Chakravarty � LSI logic, USA
Kun Young Chung � Samsung, USA
Scott Davidson � Oracle, USA
Anne E. Gattiker � IBM, USA
Kazumi Hatayama � NAIST, J
Doug Josephson � Intel Corporation, USA
Hans Manhaeve � Qstar, B
Amit Majumdar � Xilinx, USA
Erik Jan Marinissen � IMEC, B
Stephen Sunter � Mentor, USA
Baosheng Wang � AMD, USA

For more information, visit us on the web at: http://ttep.tttc-events.org/ttep/tutorials.html

The Test Technology Educational Program 2014 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)